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fedl610q340full-01 issue date: january 7, 2010 ML610Q340/ml610340 8-bit microcontroller with voice output function 1/26 general description equipped with an lapis semiconductor original 8-bit cpu nx-u8/100, the ML610Q340/ml610340 is a high-performance 8-bit cmos microcontroller that integrates a wide variety of peripherals such as a timer, synchronous serial port, and voice output function. the nx-u8/100 cpu is capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture. the microcontroller is also equipped with a flash memory that has achieved low voltage and low power consumption (at read) equivalent to mask roms, so it is best suited to battery-driven applications such as cellular phones. in addition, it has an on-chip debugging function, which allows software deb ugging/rewriting with the lsi mounted on the board. features ? cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction repertoire: 16-bit length instructions ? instruction set: transfer, arithmetic operations, comparison, logical operations, multiply/divide operations, bit manipulation, bit logical operations, jump, conditional jump, call return stack manipulation, and arithmetic shift instructions. ? built-in on-chip debugging function ? minimum instruction execution time: 0.244 ? s (@ 4.096 mhz system clock) ? internal memory ? ML610Q340 has 96-kbyte flash memory (48k ? 16-bit) built in. (including unusable 1kbyte test area) ? ml610340 has 96-kbyte mask memory (48k ? 16-bit) built in. (including unusable 1kbyte test area) ? has 512-byte ram (512 ? 8-bit) built in. ? interrupt controller ? non-maskable interrupt: 2 sources (1 internal source and 1 external sources) ? maskable interrupt: 12 sources (8 internal sources and 4 external sources) ? time-base counter ? low-speed side time-base counter ? 1ch ? high-speed side time-base counter ? 1ch ? watchdog timer ? generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second ? free-running ? selectable overflow period: 4 types (125 ms, 500 ms, 2 sec, 8 sec) ? timer ? 8-bit ? 2ch (16-bit configuration also enabled)
fedl610q340full-01 ML610Q340/340 2/26 ? voice output function ? voice synthesis method: 4-bit adpcm2 / 8-bit non-linear pcm / 8-bit pcm / 16-bit pcm ? sampling frequency: 6.4/8/10.7/12.8/16/21.3/25.6/32 khz ? speaker amplifier output power ? 1w(at 5v) ? synchronous serial port ? master/slave selectable ? lsb/msb-first selectable ? 8-bit/16-bit length selectable ? general-purpose port ? input-only port ? 4ch ? output-only port ? 4ch (those as secondary functions are also included) ? input-output port ? 4ch (those as secondary functions are also included) ? reset ? resetting by the reset_n pin ? resetting upon power-on detection ? resetting upon wdt overflow detection ? clock ? low-speed side clock internal frequency division (1/128 of the high-speed side clock) ? high-speed side clock crystal/ceramic oscillation (4.096 mhz), external clock ? power management ? halt mode: halts the execution of instructions issued by the cpu (the peripheral circuits continue operating) ? stop mode: stops low-speed and high-speed oscillation (the cpu and the peripheral circuits stop operating) ? clock gear: allows changing the frequency of the high-speed system clock by software (oscillator clock divided by 1, 2, 4, or 8) ? block control function: power down (reset registers and stop clock supply) the circuits of unused peripherals. ? shipment ? 30-pin ssop ? high-speed side clock crystal/ceramic oscillation (4.096 mhz) flash memory ML610Q340-xxxmb (blank product: ML610Q340-nnnmb) mask memory ml610340-xxxmb ? high-speed side clock external clock flash memory ML610Q340j-xxxmb (blank product: ML610Q340j-nnnmb) mask memory ml610340j-xxxmb xxx: rom code number ? gu aranteed operating range ? operating temperature: ? 40? c to +85 ? c ? operating voltage: v dd = 2.2 to 5.5 v, spv dd = 2.3 to 5.5 v (be sure to apply the same voltage to all the power supplies.)
fedl610q340full-01 ML610Q340/340 3/26 block diagram ML610Q340 f igure 1 is a block diagram of the ML610Q340. symbols with an asterisk ?*? indicate that each of them is the secondary or tertiary function of the corresponding port. figure 1 block diagram of ML610Q340 program memory (flash) 96 kbytes ssio sck0 * sin0 * sout0 * int 1 ram 512 bytes interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 wdt int 2 8-bit timer ? 2 gpio p00 to p03 p20 to p23 int 5 nmi p4 0 to p4 3 data-bus test reset_n power v ddl voicecnt sg spp spm aout reset & test alu epsw1 ? 3 psw elr1 ? 3 lr ecsr1 ? 3 dsr/csr pc greg 0 ? 15 v pp v dd v ss int 1 spv dd spv ss osc osc0 osc1 lsclk* outclk* spin
fedl610q340full-01 ML610Q340/340 4/26 ml610340 f igure 2 is a block diagram of the ml610340. symbols with an asterisk ?*? indicate that each of them is the secondary or tertiary function of the corresponding port. figure 2 block diagram of ml610340 program memory (mask) 96 kbytes ssio sck0 * sin0 * sout0 * int 1 ram 512 bytes interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 wdt int 2 8-bit timer ? 2 gpio p00 to p03 p20 to p23 int 5 nmi p4 0 to p4 3 data-bus test reset_n power v ddl voicecnt sg spp spm aout reset & test alu epsw1 ? 3 psw elr1 ? 3 lr ecsr1 ? 3 dsr/csr pc greg 0 ? 15 v dd v ss int 1 spv dd spv ss osc osc0 osc1 lsclk* outclk* spin
fedl610q340full-01 ML610Q340/340 5/26 pin configuration ML610Q340 ssop package product nc: no connection figure 3 pin configuration of ML610Q340 package product 1 12 19 30 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 15 13 14 16 17 18 v dd osc0 osc1 v ddl v pp p43 spp spm (nc) spv ss spv dd spin v ss p20 p21 p22 p42 p41 p40 v ss reset_n test p03 p02 p01 aout sg p23 nmi p00
fedl610q340full-01 ML610Q340/340 6/26 ml610340 ssop package product nc: no connection figure 4 pin configuration of ml610340 package product 1 12 19 30 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 15 13 14 16 17 18 v dd osc0 osc1 v ddl (nc) p43 spp spm (nc) spv ss spv dd spin v ss p20 p21 p22 p42 p41 p40 v ss reset_n test p03 p02 p01 aout sg p23 nmi p00
fedl610q340full-01 ML610Q340/340 7/26 list of pins primary function secondary function tertiary function pad no pin name i/o description pin name i/o description pin name i/o description 10,22 vss ? negative power supply pin ? ? ? ? ? ? 1 v dd ? positive power supply pin ? ? ? ? ? ? 4 v ddl ? power supply for internal logic (internally generated) ? ? ? ? ? ? 27 spv ss ? negative power supply pin for built-in speaker amplifier ? ? ? ? ? ? 26 spv dd ? positive power supply pin for built-in speaker amplifier ? ? ? ? ? ? 5 v pp (*) ? power supply pin for flash memory ? ? ? ? ? ? 12 test i/o input/output pin for testing ? ? ? ? ? ? 11 reset_n i reset input pin ? ? ? ? ? ? 2 osc0 i connection pin for high-speed clock oscillation ? ? ? ? ? ? 3 osc1 o connection pin for high-speed clock oscillation p11 i input port ? ? ? 24 aout o line output ? ? ? ? ? ? 25 spin i analog input to the built-in speaker amplifier ? ? ? ? ? ? 23 sg o reference power supply pin of the built-in speaker amplifier ? ? ? ? ? ? 30 spp o positive output pin of the built-in speaker amplifier ? ? ? ? ? ? 29 spm o negative output pin of the built-in speaker amplifier ? ? ? ? ? ? 17 nmi i input port, non-maskable interrupt ? ? ? ? ? ? 16 p00/exi0 i input port / external interrupt ? ? ? ? ? ? 15 p01/exi1 i input port / external interrupt ? ? ? ? ? ? 14 p02/exi2 i input port / external interrupt ? ? ? ? ? ? 13 p03/exi3 i input port / external interrupt ? ? ? ? ? ? 21 p20/led0 o output port / led drive lsclk o low-speed clock output ? ? ? 20 p21/led1 o output port / led drive outclk o high-speed clock output ? ? ? 19 p22/led2 o output port / led drive ? ? ? ? ? ? 18 p23/led3 o output port / led drive ? ? ? ? ? ?
fedl610q340full-01 ML610Q340/340 8/26 primary function secondary function tertiary function pad no pin name i/o description pin name i/o description pin name i/o description 9 p40 i/o input/output port ? ? ? sin0 i ssio0 data input 8 p41 i/o input/output port ? ? ? sck0 i/o ssio0 synchronous clock input/output 7 p42 i/o input/output port ? ? ? sout0 o ssio0 data output 6 p43 i/o input/output port ? ? ? ? ? ? *: applies to the ML610Q340.
fedl610q340full-01 ML610Q340/340 9/26 pin description pin name i/o description primary/ secondary/ tertiary logic power supply v ss ? negative power supply pin ? ? v dd ? positive power supply pin ? ? v ddl ? positive power supply pin for internal logic (internally generated) capacitors c l (see measuring circuit 1) are connected between this pin and v ss ? ? spv ss ? negative power supply pin for built-in speaker amplifier ? ? spv dd ? positive power supply pin for built-in speaker amplifier ? ? v pp (*) ? power supply pin for flash memory ? ? test test i/o input/output pin for testing. has a pull-down resistor built in. ? positive system reset_n i reset input pin . when this pin is set to a ? l ? level, the device is placed in system reset mode and the internal circuit is initialized. if after that this pin is set to a ? h ? level, program execution starts. this pin has a pull-up resistor built in. ? negative osc0 i ? ? osc1 o pins for connecting a crystal unit for high speed clock. connect a 4.096 mhz crystal unit (see measuring circuit 1) to these pins. also, connect capacitors (c dh and c gh ) between these pins and v ss as required. ? ? lsclk o low-speed clock output. this function is allocated to the secondary function of the p20 pin. secondary ? outclk o high-speed clock output. this function is allocated to the secondary function of the p21 pin. secondary ? general-purpose input port p00?p03 i general-purpose input ports. primary positive general-purpose output port p20?p23 o general-purpose output ports. provided with a secondary function. cannot be used as ports if their secondary function is used. primary positive general-purpose input/output port p40?p43 i/o general-purpose input/output ports. provided with a secondary function. cannot be used as ports if their secondary function is used. primary positive *applies to the ML610Q340.
fedl610q340full-01 ML610Q340/340 10/26 pin name i/o description primary/ secondary/ tertiary logic synchronous serial (ssio) sin0 i synchronous serial data input pin. allocated to the tertiary function of the p40 pin. tertiary positive sck0 i/o synchronous serial clock input/output pin. allocated to the tertiary function of the p41 pin. tertiary ? sout0 o synchronous serial data output pin. allocated to the tertiary function of the p42 pin. tertiary positive external interrupt nmi i external non-maskable interrupt input pin. the interrupt occurs on both the rising and falling edges. primary positive/ negative exi0?3 i external maskable interrupt input pins. it is possible, for each bit, to specify whether the interrupt is enabled and select the interrupt edge by software. allocated to the primary function of the p00?p03 pins. primary positive/ negative led drive led0?3 o nmos open drain pins to allow direct driving of led. allocated to the secondary function of the p20?p23 pins. primary positive/ negative voice output function aout o line output pin. when you use built-in speaker amplifier, connect with the spin pin. ? ? spin i analog input pin of the internal speaker amplifier. ? ? sg o reference voltage output pin of the internal speaker amplifier. ? ? spp o positive output pin of the internal speaker amplifier. ? ? spm o negative output pin of the internal speaker amplifier. ? ?
fedl610q340full-01 ML610Q340/340 11/26 termination of unused pins how to terminate unused pins pin recommended pin termination v pp open reset_n open test open spv dd v ss spv ss v ss aout open spin open sg open spp open spm open p00?p03 v dd or v ss p20?p23 open p40?p43 open note: it is recommended to configure the unused input ports and input/output ports as inputs with pull-down resistors/pull-up resistors or outputs since the supply current may become excessively large if those pins are left open in the high impedance input setting.
fedl610q340full-01 ML610Q340/340 12/26 electrical characteristics absolute maximum ratings (v ss = spv ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25 ?c ? 0.3 to +7.0 v power supply voltage 2 spv dd ta = 25 ?c ? 0.3 to +7.0 v power supply voltage 3 v ddl ta = 25 ?c ? 0.3 to +3.6 v power supply voltage 4 v pp ta = 25 ?c ? 0.3 to +9.5 v input voltage v in ta = 25 ?c ? 0.3 to v dd +0.3 v output voltage v out ta = 25 ?c ? 0.3 to v dd +0.3 v output current 1 i out1 p4, ta = 25 ?c ? 12 to +11 ma output current 2 i out2 p2, ta = 25 ?c ? 12 to +20 ma power dissipation pd ta = 25 ? c 861 mw storage temperature t stg D ? 55 to +150 ?c recommended operating conditions (v ss = spv ss = 0v) parameter symbol condition range unit operating temperature t op D ? 40 to +85 ?c v dd D 2.2 to 5.5 operating voltage spv dd D 2.3 to 5.5 v operating frequency (cpu) f op D 437k to 4.2m hz high-speed crystal/ceramic oscillation frequency f xth D 4.0m, 4.096m hz c dh D 15 to 32 high-speed crystal oscillation external capacitor c gh D 15 to 32 pf capacitor externally connected to v ddl pin c l D 10? 30% ? f capacitor externally connected to sg pin c sg D 0.1 ? 30% ? f
fedl610q340full-01 ML610Q340/340 13/26 flash memory operating conditions (v ss = spv ss = 0v) parameter symbol condition range unit operating temperature t op at write/erase 0 to +40 ?c v dd at write/erase 2.7 to 3.6 v ddl at write/erase (*1) 2.5 to 2.75 operating voltage v pp at write/erase (*1) 7.7 to 8.3 v maximum rewrite count c ep D 80 times data retention period y dr D 10 years *1: when writing data to, or erasing data from, flash rom, it is necessary to apply a voltage within the range specified above to the v ddl pin. dc characteristics (1 of 5) (v dd = spv dd = 2.2 to 5.5v, v ss = spv ss = 0v, ta = ? 40 to +85 ? c, unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit high-speed oscillation start time t xth D D 2 20 ms reset pulse width p rst D 100 D D reset noise rejection pulse width p nrst D D D 0.4 ? s time from power-on reset to power-up t por D D D 10 ms 1 reset reset_n reset by reset_n pin vdd 0.9 ? v dd 0.1 ? v dd t por power-on reset p rst vil1 vil1
fedl610q340full-01 ML610Q340/340 14/26 dc characteristics (2 of 5) (v dd = spv dd = 2.3 to 5.5v, v ss = spv ss = 0v, ta = ? 40 to +85 ? c, unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit line amplifier output load resistance r la at 1/2v dd output 10 ? ? k ? line amplifier output voltage range v ad at output load v dd ? 1/6 ? v dd ? 5/6 v sg output voltage v sg D 0.95 ? v dd /2 dv dd /2 1.05 ? v dd /2 v sg output resistance r sg D 57 96 135 k ? spm, spp output load resistance r lsp D 8 D D ? pspo1 spv dd = 3.3v, f = 1khz, rspo = 8 ? , thd ? 10% at spin input ? 0.5 ? w speaker amplifier output power pspo2 spv dd = 5.0v, f = 1khz, rspo = 8 ? , thd ? 10% at spin input ? 1 ? w output offset voltage between spm and spp with no signal present vof spv dd =3.0v, spin ? spm gain = +6db with a load of 8 ? ? 50 ? +50 mv 1
fedl610q340full-01 ML610Q340/340 15/26 dc characteristics (3 of 5) ML610Q340 (v dd = spv dd = 2.2 to 5.5v, v ss = spv ss = 0v, ta = ? 40 to +85 ? c, unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit ta ? +40 ?c D 0.5 2.0 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped ta ? +85 ?c D 0.5 8 ? a v dd = spv dd = 3.0v D 1.7 4 supply current 4 idd4 cpu: running at 4.096mhz crystal/ceramic oscillating mode * 1 v dd = spv dd = 5.0v D 2.2 4 v dd = spv dd = 3.0v D 3 12 supply current 5 idd5 cpu: running at 4.096mhz crystal/ceramic oscillating mode * 1 during voice playback (no output load) v dd = spv dd = 5.0v D 8 12 ma 1 * 1 : use 4.096mhz crystal oscillator chc49sfwb (kyocera). dc characteristics ml610340 (v dd = spv dd = 2.2 to 5.5v, v ss = spv ss = 0v, ta = ? 40 to +85 ? c, unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit ta ? +40 ?c D 0.5 2.0 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped ta ? +85 ?c D 0.5 8 ? a v dd = spv dd = 3.0v D 0.75 4 supply current 4 idd4 cpu: running at 4.096mhz crystal/ceramic oscillating mode * 1 v dd = spv dd = 5.0v D 1.5 4 v dd = spv dd = 3.0v D 3 12 supply current 5 idd5 cpu: running at 4.096mhz crystal/ceramic oscillating mode * 1 during voice playback (no output load) v dd = spv dd = 5.0v D 8 12 ma 1 * 1 : use 4.096mhz crystal oscillator chc49sfwb (kyocera).
fedl610q340full-01 ML610Q340/340 16/26 dc characteristics (4 of 5) (v dd = spv dd = 2.2 to 5.5v, v ss = spv ss = 0v, ta = ? 40 to +85 ? c, unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit voh1 ioh1 = ? 0.5ma v dd ? 0.5 D D output voltage 1 (p20?p23) (p40?p43) vol1 iol1 = +0.5ma D D 0.5 iol2 = +5ma v dd ? 2.2v D D 0.5 output voltage 2 (p20?p23) vol2 when led drive mode is selected iol2 = +8ma v dd ? 2.3v D D 0.5 v 2 iooh voh = v dd (in high-impedance state) D D 1 output leakage current (p20?p23) (p40?p43) iool vol = v ss (in high-impedance state) ? 1 D D ? a 3 iih1 vih1 = v dd 0 D ? 1 input current 1 (reset_n) iil1 vil1 = v ss ? 1500 ? 300 ? 20 iih2 vih2 = v dd (when pulled down) 2 30 250 iil2 vil2 = v ss (when pulled up) ? 250 ? 30 ? 2 iih2z vih2 = v dd (in high-impedance state) D D 1 input current 2 (nmi) (p00?p03) (p40?p43) iil2z vil2 = v ss (in high-impedance state) ? 1 D D iih3 vih3 = v dd 20? 300 1500 input current 3 (test) iil3 vil3 = v ss -1 ? D D ? a 4
fedl610q340full-01 ML610Q340/340 17/26 dc characteristics (5 of 5) (v dd = spv dd = 2.2 to 5.5v, v ss = spv ss = 0v, ta = ? 40 to +85 ? c, unless otherwise specified) parameter symbol condition min. typ. max. unit measuring circuit vih1 D 0.7 ? v dd D v dd input voltage 1 (reset_n) (test) (nmi) (p00?p03) (p11) (p40?p43) vil1 D 0 D 0.3 ? v dd hysteresis width (reset_n) (test) (nmi) (p00?p03) (p11) (p40?p43) ? vt D 0.05? v dd D 0.4 ? v dd v 5 input pin capacitance (nmi) (p00?p03) (p11) (p40?p43) cin f = 10khz v rms = 50mv ta = 25 ?c D D 10 pf D hysteresis width ? v t input signal internal signal v dd v ss v ss v ddl
fedl610q340full-01 ML610Q340/340 18/26 measuring circuits measuring circuit 1 measuring circuit 2 osc0 p11/osc1 4.096mhz crystal unit c gh c dh a v dd v ddl c l sg c sg v ss spv ss c4 c3 c2 c1 c 12 c 34 c v : 1 ? f c l : 10 ? f c sg : 0.1 ? f c gh : 24 pf c dh : 24 pf 4.096 mhz crystal unit: hc49sfwb (kyocera) c v spv dd v v dd v ss v ddl spv ss vih vil *1: input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. (*2) (*1) spv dd input pins output pins
fedl610q340full-01 ML610Q340/340 19/26 measuring circuit 3 measuring circuit 4 a v dd v ss v ddl spv ss vih vil *1: input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. (*2) (*1) spv dd input pins output pins a v dd v ss v ddl spv ss *3: measured at the specified input pins. (*3) spv dd input pins output pins
fedl610q340full-01 ML610Q340/340 20/26 measuring circuit 5 v dd spv dd v ss v ddl spv ss vih vil *1: input logic circuit to determine the specified measuring conditions. (*1) output pins waveform monitoring input pins
fedl610q340full-01 ML610Q340/340 21/26 ac characteristics (external interrupt) (v dd = spv dd = 2.2 to 5.5v, v ss = spv ss = 0v, ta = ? 40 to +85 ? c, unless otherwise specified) parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation 2.5 ? sysclk D 3.5 ? sysclk ? s t nul p00?p03 (rising-edge interrupt) p00?p03 (falling-edge interrupt) nmi, p00?p03 (both-edge interrupt) t nul t nul
fedl610q340full-01 ML610Q340/340 22/26 ac characteristics (synch r onous serial port) (v dd = spv dd = 2.2 to 5.5v, v ss = spv ss = 0v, ta = ? 40 to +85 ? c, unless otherwise specified) parameter symbol condition min. typ. max. unit high-speed oscillation stopped 10 D D ? s sck input cycle (slave mode) t scyc during high-speed oscillation 500 D D ns sck output cycle (master mode) t scyc D D sck (*1) D sec high-speed oscillation stopped 4 D D ? s sck input pulse width (slave mode) t sw during high-speed oscillation 200 D D ns sck output pulse width (master mode) t sw D sck (*1) ? 0.4 sck (*1) ? 0.5 sck (*1) ? 0.6 sec sout output delay time (slave mode) t sd D D D 180 ns sout output delay time (master mode) t sd D D D 80 ns sin input setup time (slave mode) t ss D 50 D D ns sin input hold time t sh D 50 D D ns *1: clock period selected by s0ck3?0 of the serial port 0 mode register (sio0mod1) t sd sck0* sin0* sout0* *: indicates the secondary function of the corresponding port. t sd t ss t sh t sw t sw t scyc
fedl610q340full-01 ML610Q340/340 23/26 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). the heat resistance (example) of this lsi is shown below. heat resistance ( ja) changes with the size and the number of layers of a substrate. die pad on the back of a package partial ground contact area 100% pcb jedec w/l/t 76.2/114.5/1.6 mm pcb layer 4l air cooling conditions calm 0m/sec heat resistance ja 45[ /w] power consumption of chip pmax at outputpower 1w (5v) 0.818[w] power consumption of chip pmax at outputpower 0.5w (3.3v) 0.283[w] tjmax of this lsi is 125 . tjmax is expressed with the following formulas. tjmax = tamax + ja pmax ( unit: mm )
fedl610q340full-01 ML610Q340/340 24/26 mounting area for package lead soldering to pcb (reference data) is shown below. die pad on the back of a package should connect with the substrate of opening or a v ss for heat dissipation.
fedl610q340full-01 ML610Q340/340 25/26 revision history page document no. date previous edition current edition description fedl610q340full-01 jan 7, 2010 ? ? formally edition 1
fedl610q340full-01 ML610Q340/340 26/26 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the info rmation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failur e or malfunction of which may result in a direct threat to human life or create a risk of human injury (suc h as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2008 - 2011 lapis semiconductor co., ltd.

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